Modern Computers and technological evolution. The role of performance. Introduction to Assembly languages. The Risc V language. The simulator. Logic circuits (combinatorial and sequential). Fundamentals of number representation and binary arithmetic. The design of an ALU. Multiplication and division. Floating point numbers. Design of a CPU. Exceptions. Pipelining. Memory Hierarchies, Caches, Virtual memory.
David A Patterson, John L Hennessy, STRUTTURA E PROGETTO DEI CALCOLATORI - Progettare con RISC-V. Italian Edition by Alberto Borghese. Zanichelli, 2019 . ISBN: 9788808820594
C. Bolchini, C. Brandolese, F. Salice e D. Sciuto. Reti logiche, 2/e, Apogeo, 19 settembre 2013.
Learning Objectives
The course aims to provide the basic elements in order to understand computer architecture and the interface between this and the higher levels of abstraction of a computation system. Moreover, teaching an assembly language (RISC V) intends to give the elements to understand assembly languages and the interface that they constitute between hardware architecture and the higher level of abstraction of a computation system. The description of both the Processor structure and the system organization including memories aims at providing a global perception of computing systems.
Prerequisites
None
Teaching Methods
CFU: 12
Total hours of the course: 300
Hours reserved to private study and other individual formative activities: 194
Contact hours for: Lectures (hours): 82Contact hours for: Laboratory (hours): 20
Contact hours for: Laboratory-field/practice (hours): 0
Seminars (hours): 0
Stages: 0
Intermediate examinations: 4
Further information
Frequency of lectures, practice and lab: STRONGLY Recommended
Prof. Andrea Ceccarelli,
by appointment. Contact professor by phone number or e-mail
(andrea.ceccarelli@unifi.it).
DiMaI, Universita' di Firenze, Viale Morgagni, 65 - 50134 Firenze
Dott. Tommaso Zoppi,
by appointment. Contact professor by phone number or e-mail
(tommaso.zoppi@unifi.it).
DiMai, Universita' di Firenze, Viale Morgagni, 65 - 50134 Firenze
Type of Assessment
Traditional Method
- Project on the lab activity (Assembly RISCV)
- Written exam + oral interview on the topics of the course, to be taken in the same session.
Both the written exam and the oral interview can be taken only if the project has been evaluated as positive. The oral interview can be taken only if the written exam is at least sufficient (mark >= 18), and regards both theory and lab topics. The final mark for the exam is obtained as a combination of the project, written exam and oral interview, but is not computed as an average of the three individual marks.
"Prove Intermedie" Method
(Once in the university career)
As an alternative to the traditional method, students that attend the course for the first time, or who have already attended but have never attempted the full exam or used this method in previous years, will have two opportunities for "prove intermedie" during the winter break of the lessons in February 2023.
These "prove intermedie" are written exams that focus on all the theory and laboratory topics covered in the first semester. Each prova intermedia is composed of 5/6 exercises and is evaluated positive with a mark >= 18. The student can participate in both tests: however, the mark the student gets in the second "prova intermedia" will override any result obtained in the first "prova intermedia" (even if evaluated positively).
A positive mark in either of the two "prove intermedie" in February 2023 guarantees exemption from written exams up to the February 2024 session (included). In order to register for the final exam, the project must be delivered and evaluated positively, and there will be only the oral interview, which will mostly focus on the topics of the 2nd semester. Please note that during the oral interview, teachers may ask about topics from the first semester which correspond to exercises of the "prova intermedia" that have been evaluated poorly, or if the answers of the students during the interview raise severe concerns about their understanding of the topics of the 1st semester.
The final mark for the exam is obtained as a combination of the project, written exam and oral interview, but is not computed as an average of the three individual marks.
Course program
Modern computers and technological evolution.
The role of performance.
Combinatorial logic circuits: specification, synthesis, minimization.
Clock and memory elements.
Finite state machine and sequential circuits.
Introduction to assembly language of RISC-V system.
Language simulator.
Lab activities: programming in assembly.
Fundamental notions of numbers representation and binary arithmetic.
Design of an ALU.
Multiplication and division.
Floating points numbers.
RISC-V processor: Design of a single cycle CPU: data path and control path.
Enhancing performance by Pipeling: data paths and control path. Pipeline criticalities and additional processor components for their solution, exceptions.
Memory hierarchy, caches and
Basics on virtual memory.